1. Field of the Invention
The present invention generally relates to systems and methods for generating information for use in a wafer inspection process based on empirical image information.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
Inspection generally involves generating some output (e.g., images, signals, etc.) for a wafer by directing light or electrons to the wafer and detecting the light or electrons from the wafer. Once the output has been generated, defect detection is typically performed by applying some defect detection method and/or algorithm to the output. Parameters used to generate the output (e.g., optical or electron beam hardware settings) and parameters used to detect the defects (e.g., defect detection algorithm settings) are typically determined based on characteristics of the wafer and defects to be detected thereon. Most often, the goal of inspection recipe setup is to determine the parameters that will provide the highest sensitivity to defects of interest while suppressing detection of nuisance and noise on the wafer. Determining the appropriate inspection parameters becomes much more difficult when the characteristics of the wafer vary across the wafer. Examples of wafers whose characteristics vary across the wafer include, but are not limited to, patterned wafers (on which the patterned features vary as a function of within wafer positions) and wafers having some source of non-defect-related noise that varies across the wafers.
Many different methods and systems have, therefore, been created that can be used to determine and vary inspection parameters across a wafer. For example, information about the patterns being formed on a wafer can be used to determine and apply different inspection parameters across a wafer. The pattern information may be acquired using physical design data and electronic design automation (EDA) design rule check type tools. The pattern information can be searched for different types of patterns that may affect the inspection process using, for example, a rule-based search and/or a pattern search. In addition, pattern information from any source such as process modeling, statistical analysis of test results, or failure analysis may be used to determine and apply inspection parameters that vary across the wafer.
There are, however, a number of disadvantages of the currently used methods for wafer inspection setup. For example, the current approaches assume that pattern noise is well-behaved and uniform across wafers. However, due to systematic process signatures this is often not the case. In addition, the care area sets (where “care areas” are generally defined as the areas in the pattern and/or on the wafer that a user cares about and are therefore inspected) determined from pattern information may be too numerous relative to the capacity of the inspector to treat them each individually. The combination of care area groups may therefore be required. Such care area group combination may typically be performed in an ad hoc fashion today. Another disadvantage is that care area sets may often contain an inhomogeneous set of patterns which in fact have very different noise characteristics.
Accordingly, it would be advantageous to develop systems and methods for generating information for use in a wafer inspection process that do not have one or more of the disadvantages described above.